1. Field of the Invention
The present invention relates to a pulse signal generator, and to a method of generating a pulse signal.
2. Description of Related Art
In recent years, with an aim to perform dimming control of illumination or liquid crystal backlight, a pulse width modulation (PWM) signal is frequently used. When a pulse signal is used for the above intended purpose, it is necessary to change a period of the pulse signal according to a resonance frequency of an inverter, a refresh rate of a screen, or the like. In this case, even when the period of the pulse signal is changed, it is necessary to retain the duty ratio and the number of steps. On the other hand, with the higher function of products, a demand is made to reduce a load on a central processing unit (CPU). For that reason, a pulse generating device is demanded which is capable of retaining the duty ratio and the number of steps without exerting a load on the CPU when the period of the pulse signal is changed.
An example of the solution has been proposed in JP-A-2002-141787. FIG. 13 shows a block diagram for explaining a pulse generator circuit disclosed in JP-A-2002-141787. The pulse generator circuit shown in FIG. 13 is made up of counter circuits 1, 2, and an RS flip-flop circuit 3. The counter 1 and the counter 2 are controlled by a CPU (not illustrated).
In the disclosure of JP-A-2002-141787, when the counter 1 is selected by the CPU, the counter 1 is set with (a pulse off time (t1))/(a reference clock period) as a count target set value. Likewise, when the counter 2 is selected by the CPU, the counter 2 is set with (a pulse period (t1+t2))/(a reference clock period) as the count target set value. The pulse off time means a period of time during which the pulse signal outputs a low level per cycle.
Also, the count operation of the counters 1 and 2 is executed on the basis of a reference clock. The count operation of each counter starts when a START signal input to an input terminal ST of each counter is rendered active.
FIG. 14 shows a timing chart of the pulse generator circuit disclosed in JP-A-2002-141787. An upper diagram of FIG. 14 shows a timing chart in which the axis of ordinate is a counter value whereas the axis of abscissa is a time value. A lower diagram of FIG. 14 shows a signal change of an output signal OUT on the same time axis as that of the upper diagram. First, an initial state of the output signal of the RS flip-flop 3 is set to the low level. In the counter 1, when a value counted by the reference clock reaches the count target set value, a count complete signal is outputted from an output terminal O1 of the counter 1. The signal output from the counter 1 is inputted to an input terminal S of the RS flip-flop 3. As a result, the output signal of the RS flip-flop 3 changes over from the low level to a high level.
Likewise, in the counter 2, when the value counted by the reference clock reaches the count target set value, the count complete signal is outputted from an output terminal O2 of the counter 2. The signal output from the counter 2 is inputted to an input terminal R of the RS flip-flop 3. As a result, the output signal of the RS flip-flop 3 changes over from the high level to the low level.
As described above, a pulse having the duty ratio and the frequency in an arbitrary pulse off time can be generated according to (the set value of the counter 1)/(the set value of the counter 2). In this case, the period and frequency of the pulse are determined by the counter 2. Also, the duty ratio in the off time of the pulse output signal is determined according to the set value of the counter 1 and the set value of the counter 2.
Further, JP-A-HEI5-260798 discloses a circuit configuration which is capable of changing only the duty ratio of the pulse signal. FIG. 15 shows a block diagram of a torque control circuit for a stepping motor disclosed in Patent Document 2. The block diagram shown in FIG. 15 is made up of a sawtooth generator circuit 501, a digital-to-analog (D/A) converter 505, a comparator 502, a driver 503, and a stepping motor 504. In this case, only parts related to the art of the present invention in the block diagram shown in FIG. 15 will be described.
In the block diagram shown in FIG. 15, a sawtooth wave having a given period output from the sawtooth generator circuit 501 is inputted to a noninverting input terminal of the comparator 502. Also, a control signal output from the D/A converter 505 is inputted to an inverting input terminal of the comparator 502.
In this case, when a voltage level of the noninverting input signal is larger than a voltage level of the inverting input signal, a signal of high level is outputted from the comparator 502. Also, when the voltage level of the noninverting input signal is smaller than the voltage level of the inverting input signal, a signal of low level is outputted from the comparator 502. That is, the voltage level of the control signal output from the D/A converter 505 is controlled, thereby enabling only the duty ratio of the pulse signal output from the comparator 502 to be changed.